A high-speed serial receiver samples incoming data symbols at some phase of the high-speed clock generated from a phase-locked loop (PLL). The PLL uses a reference clock to produce the high-speed clock. The edge transitions (i.e., the recovered clock) between incoming data symbols can be recovered using the high-speed clock. To properly sample the incoming data symbols, the receiver should sample the incoming data symbols between the edge transitions in the stream of incoming data symbols. The range of sampling phases for which the high-speed serial receiver properly recovers the incoming data symbols gives the margin for the sampling phase.
To check that the data symbols actually captured by the high-speed serial receiver match the data symbols that the external test equipment transmits to the high-speed serial receiver, the captured data symbols must be looped back to the external test equipment. However, it is time consuming and difficult to determine the margin of the sampling phase because external test equipment is required and because the tested receiver must generally include a transmitter supporting a loopback mode for returning the captured data symbols. Further, in order to determine whether a phase of a clock signal is acceptable for receiving data, numerous points must be checked. These numerous points must be checked for each phase of a plurality of available phases which could be used for receiving data. The requirement to check many points for a number of phases of a clock signal further increases the testing time for a receiver.